The microprocessor DSP33F in the microcomputer protection device design and application

1 Introduction
In recent years, a variety of integrated single-chip DSP performance have been greatly improved, more and more software and development tools, DSP devices and technology easier to use, the price for the majority of users to accept the the Microchip company launched the digital The signal processor DSP33F A / D conversion, communication, watchdog, protection and data storage, also supports SPI mode and I2C mode data transmission, easy to expand capacity. Therefore, the development DSP33F microcomputer-based protection device, not only to enhance the overall performance of the protection system and the versatility of the hardware platform, but also to reduce development time, reduce development and hardware costs, to improve the level of stable operation of the power system has a certain significance.
2 digital signal the controller DSP33F series About
DSP33F series is a high-performance 16-bit digital signal controllers, with the expansion of digital signal processor (DSP) functionality and high-performance 16-bit microcontroller (MCU) architecture. It is a 16-bit modified Harvard architecture RISC device, the integration of high-speed computing power of a high-performance 16-bit microcontroller control strengths and digital signal processor, a high-performance digital signal controller (DSC). DSP33F series devices have the following characteristics:
(1) DSP cores and instruction system DSP33F DSP engine has a high-speed 17 × 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional shift , its computing speed of up to 40 MI / s, the instruction word is 24 instruction system consists of MCU instruction set and DSP instruction set. In addition, these instructions do the C language compiler specifically optimized programs written in the C language code efficiency is high. DSP33F deviation allowable working voltage of ± 10%, operating voltage of 3.0 to 3.6 V.
(2) direct memory access (DMA) and interrupt capability DSP33F internal integrated 8-channel direct memory access module allows the CPU to execute code during the transmission of data between the RAM and peripherals, no cycle. 2 KB dual-ported DMA buffer area (DMA RAM), used to store data transferred via DMA. DMA interrupt sources set via software, so as to meet the design requirements. DSP33F exception handling structure, containing up to 118 prioritized interrupt vector interrupt priority is divided into seven. Up to 67 interrupt sources, five external interrupt 5 processor exceptions.
(3) the storage space and peripheral devices and program counter is 23 bits wide, 4 Mx24 bit addressable program memory space. 2 data area addressed; DSP instructions and the the MCU instruction and data space overall as 64Kx8 bit addressing. DSP33F internal integrated SRAM and Flash memory devices necessary to provide 10 bit and 12-bit A / D converter module (optional), 8-bit watchdog, UART, SPI, I2C, CAN communication module.
(4) development tools Microchip's High Performance Development System support DSP33F series controllers. The development system includes the MPLAB integrated development environment (IDE), MPLAB C30 C compiler, MPIAB SIM 30 software emulator MPIABICD 2-Circuit Debugger and MPLAB ICE 4000 in-circuit emulator. DSP33F series digital signal controller is also equipped with a series of applications library.
3 DSP33F microcomputer protection hardware system
The device according to the functions into the CPU module, AC plug, digital I / O microprocessor-based protection, communications, human-machine interface unit and power supply unit. Communication interface to connect directly with the host computer or communication manager, the man-machine interface with 128x64 dot-matrix liquid crystal display and a dedicated keyboard, display large amount of information, ease of operation, hardware design block diagram in Figure 1 below. The microcomputer protection device has 16 binary inputs, 16 open volume, 15 channel analog CPU module block diagram shown in Figure 2. Because DSP33F powerful computing power of juice and perfect control function can be individually complete the calculation, control, communications, human-machine interfaces and functions to reduce the number of devices to simplify the hardware structure. Because of DSP33F internal integrated RAM, Flash A / D converter, outside with little expansion circuit, further simplify the hardware structure, the basic realization of the bus not the chip did not count, and greatly improve the protection of anti-jamming device and reliable sex.
The 3.1 memory expansion and the real-time clock interface
DSP33Fj256GP710 internal integrated 30 KB of SRAM is used as a data storage space enhanced 256 KB Flash as a program or data storage area. Extended external storage space of 1 MB computer protection, storage protection setting, event logging, and fault recording data needs more storage space, so the device through the SPI bus serial flash memory AT45DB081 connected with DSP33FJ256GP71O. AT45DB081 operating voltage. 7 ~ 3.6 V, Rewritable in the system and is compatible with SPI Flash memory. Within 4096 pages of 264 bytes per page, the total 8MB of main memory capacity, and two 264-byte SRAM data cache. The interface design circuits AT45DB081 with DSP33FJ256GP710 shown in Figure 3. 3 DSP33Fj256GP710 the SDO1, SOI1, SCK1 AT45DB081 serial input (SI), serial output (SO) and clock (SCK) pin connected, RE4, RE2, RE5, RE6 with AT45DB081 chip select ( CS), reset (RESET), busy status (RDY / BUSY) and write-protect (WP) pin is connected. The DSP33F by RE5 the read AT45DB081 busy status pin to determine the memory is idle, if RE5 to "1" indicates that the memory is idle, otherwise the memory is busy. When the memory is idle, the through RE4 pin output "0" as the memory chip select signals sent through the SPI command word, select the memory after the completion of read and write operations on the corresponding AT45DB081. Microcomputer Protection need to configure the three fixed value, and stored in three different intervals, the runtime check its set value is correct. To this end, AT45DB081 space allocated as follows: given value, the control word, the factory setting and adjustment coefficient is divided into four zones, stored in AT45DB081 the 0 to 9, first for AT45DB081 the first 0,1 2, respectively, the storage protection device 1,2,3 given value; the second region AT45DB081 3,4,5, respectively store the protection device 1, 2,3 a fixed value; third zone 6,7,8 page of the AT45DB081 storage protection devices 1.2.3 setting; the Area 4 AT45DB081 9 storage adjustment coefficient. The event records are stored in AT45DB081 10 to 1 000. Fault recorder data is stored in AT45DB081 1 001 to 4000 pages.
PCF8583 serial bus expansion, DSP I2C clock line SCL and data line SDA completed PCF8583 parameter settings, date and time to read while PCF8583 has a simple interface, take up less DSP resources and high reliability, and even power down time count. Extended clock device used to record the system time. In addition, in order to avoid the device frequently read and write EEPROM protection device frequently read and write signals, such as accidents, trailers, pulse rate, number of restarts, device failure signal and exit signs are stored in RAM registers, clock devices read current time, while also calling these contents, the device power off again able to obtain this information on power.
3.2 based on the DMA's A / D converter
32 DSP33FJ256GP710 integrated high-precision 12 bit A / D converter module, the conversion speed of up to 1 Ms / s, and the flexibility to set the sampling channel. Sampling choice of both manual and automatic mode, the channel stop sampling and start conversion variety, such as manually clear SAMP to start sampling internal counter count trigger sampling, timer Timer3 overflow trigger sampling interrupt pin INTO trigger. Timer Timer3 overflow sampling sentinel sampling for protection device. The A / D conversion using direct memory access (DMA) mode. Directly after the end of the sampling period, the data stored in the DMA RAM (2 KB), do not take up CPU cycles. After the end of the A / D converter, and the data has been stored in the DMA RAM DMA interrupt, the register AD1CON2 can be used multiple sampling after the end of an interrupt is generated. 15-channel analog device were collected using automatic sampling and Timer3 trigger conversion mode, the conversion is triggered once in each sampling period, all 15 Road, an interrupt is generated after the end of the sampling period and time to read all 15 road data from DMA RAM. In this mode, the CPU simply start an A / D conversion, in the case of the CPU instruction cycle, sampling data from the peripheral dump in RAM through DMA, sample processing efficiency is greatly improved. To the CPU enough time to calculate and fault judgment is vacated.
3.3 Ethernet interface extension
The Ethernet interface extensions circuit is shown in Figure 4. This device uses the I / O port simulation SPI master controller ENC28J60 connection, ENC28J60 to close at least one interrupt signal informs DSP33F, issued by the INT pin. SO host read command pin, SI pin host write command. Microchip provides specific DSP33F family of digital signal controllers embedded TCP / IP protocol stack CMX-MicroNet the protocol stack optimized for DSP33F family of devices Flash and RAM resources, provides software for the realization of the Ethernet function supported. The protocol stack can either be run separately and can also be used in embedded real-time operating system (RTOS). Microchip CMX-MicroNet protocol stack is a layered structure, users can be realized in the case of not very familiar with the TCP / IP network applications.
In the main program, the watchdog time of DSP33F own initialization, and that is to be set: two 8-bit counter WDT Prescaler A, WDT Prescaler B, overflow time can be adjusted between 2 ms ~ 16 s. In the timer initialization of DSP33F be considered DSP33FJ256GP710 has nine 16-bit timer. The device software using three timers: T1, T3 and T5. The timer T1 interrupt time to complete the reading and writing of the clock to 1 ms, open into the amount collected, open the amount of output switch displacement event logging functions.
Timer T3 interrupt the completion of the start of the A / D converter. Not take up CPU cycles through the DMA mode, the sample data stored in the DMA RAM, to avoid the exchange of data between the CPU and peripherals and take up valuable CPU time, to make the program run faster the sampling data read in DMAO interrupt. T5 interrupt complete protection calculations and judgments.
Downstream to modify the protection given complete computer protection device upload switch transceiver two communication interrupt function, mainly to protect the setting, event logging, and remote measurement (current, voltage, active power, reactive power, power factor, etc.) value, time information and the remote control operation. This device is used for communication IEC60870-5-103 transmission the Statute and Mdbus Statute (optional), in order to achieve a standardized communication interface requirements.
5 anti-jamming design the DSP33F-based protection device
In the microcomputer protection device work environment, electromagnetic interference (such as lightning) is very serious, system failure, system equipment misuse and control, overcurrent and surge interference and so may invade the protective device. Internal microcomputer protection device, due to the action of the auxiliary relay or DC converter converts the high-frequency signal, and can also interfere. The characteristics of these disturbances is high frequency, large amplitude and short duration, through a variety of channels penetrated microcomputer protection device in the electronic circuit, and interfere with the normal operation of the microcomputer protection. DSP33F internal WDT module integrated, specialized clock signal provided by the internal oscillator circuit. If no clear pulse, it generates a fixed frequency of the output pulse, so that the entire CPU system reset restart. Start Watchdog Timer settings can be enabled simply MPLAB ICD 2 integrated development environment watchdog. To enhance the anti-jamming performance, the software is also an additional four unshielded interrupt error-handling function to handle the ground to take on the crystal, address, stack and arithmetic errors in the hardware anti-jamming measures, isolation, shielding measures effectively to ensure that the device's electromagnetic compatibility .
6 Conclusion
Studied a new microcomputer relay protection based on DSP33F microprocessor hardware platform, gives details of the system hardware design and software process. The program structure is simple, cost-effective and high reliability and development cycle power plants and substations sets microcomputer protection device on the hardware and software platform developed by the the national relay testing center type test, and has been put into operation in the field, the technical indicators meet the relevant industry standards and site requirements.