LED-based video display board design

Abstract: At present, all the top video display board manufacturers are using different color pixel size of the LED video display module, structurally similar but distinctive. Maxim has applied its unique technology in this field, introduced the MAX6974 LED drivers, combined with low-cost, medium-sized FPGA chip to provide a LED-based video display board reference design.
Outline
 A rough estimate, the global installation of large LED video display board has reached tens of thousands. With the decline in the price of the overall system, operating processes, simplified display panel, LED video display board will be further spread. This application note describes a basic low-cost LED video display module. This new design uses low-cost FPGA chips to complete the distribution of digital video bit stream, the MAX6974 LED Driver constitute QVGA (320 x 240) resolution, LED video displays. The display board can be controlled via a PC, as a secondary monitor to display any text, graphics or multimedia message.
 The current structure of LED display panels
 Currently, all the top video display board manufacturers are using different color pixel size of the LED video display module, structurally similar but distinctive. Video display module about the size of pixels in the range of 256-15552, by the vendor. Spliced ​​together a video display module side can reach a few meters form the video wall (Figure 1). Each video display module with a different PCB, PCB LED installed on their drive. In addition, the installation of LED driver is also installed on the PCB and FPGA chip video buffer.
 For a video wall, video display modules commonly used coaxial cable connection. Through the optical fiber connected to the video wall control and video processing unit. Control unit is used to configure the video display module, the right to select the video source. Video processor receives the selected video signal format conversion after the correct data is sent to the corresponding pixel position. Video processor data cache, and also the need for proportional regulation. The application of the controller and the video processor unit is professional equipment, the price may be very high.

图1. 目前LED视频显示板的系统架构

Figure 1. At present, LED video display board system architecture

 Maxim program
 MAX6974 LED driver using the unique features can be combined with a low-cost, medium-sized FPGA to build a LED video display board, through the PC control system (Figure 2). Additional video interface using a PC card can support different video sources, which form a complete LED video display board, only a few electronic components, without specialized equipment.


图2. 基于MAX6974的LED视频显示板系统架构
Detailed picture (PDF, 12kB)
Figure 2 based on MAX6974 LED video display board system architecture
   MAX6974 LED Driver features
  MAX6974 LED driver designed for LED video display board applications. Each LED driver 24 includes the same constant current, PWM LED driver port to drive 8 or 16 (dual mode) RGB pixels. To meet the video or static images, remove black screen phenomenon, the PWM chip rate is very high. When the video refresh rate of 60fps (frames per second) when, PWM rate of about 7680Hz. MAX6974 data input interface includes a clock and a pair of LVDS LVDS data output interface can also be data series MAX6974 LED drivers to provide higher data bits, the clock also includes LVDS and LVDS data pairs. According to the video refresh rate and clock frequency can be hundreds of pieces MAX6974 devices connected via LVDS interface. Use this interface, LED drivers, and video display module PCB can be several feet long between the twisted-pair cable connected.
   MAX6974 are three ways to control the brightness of each LED. First, each individual LED (red, green or blue) has a 12-bit PWM brightness control, much higher than the DVI ™ interface specifications for each 8-bit color resolution, and the remaining bits can be used for contrast adjustment, to adapt to different ambient light conditions; second, seven PDM is used to adjust the brightness control all the LED drive ports, these bits can be used for brightness control of PDM. Finally, each port LED driver with constant step size of 256 controls (6mA to 30mA). These calibration steps used to configure the different temperatures required by the video color.
  Based on MAX6974 LED video display board structure detailed design
The LED video display board reference design uses an FPGA to achieve the distribution of video data, it can capture the control frame, and forwards them directly to each piece MAX6974 LED driver inside the corresponding register. Figure 3 shows a QVGA resolution (320 x 240) reference design block diagram, using TFP401 DVI receiver, used to store the EDID AT24C02 EEPROM, EP2C20 FPGA and 9600 MAX6974 LED drivers to drive 76,800 a OVSRRGBCC3 RGB LED .

图3. 参考设计功能框图

 Detailed picture (PDF, 68kB)
 Figure 3 reference design block diagram
  Diagram on the left of the DVI signal from the TFP401 DVI receiver, AT24C02 EEPROM provides EDID to the Windows ® operating system. Deserializer and the TMDS signal after decoding the signal sent to the EP2C20. Rearrange the video bit by 5 to 32Mbps speed LVDS channel LED video modules delivered to the PCB out. Contains two on each LVDS differential pair, CLKI (O) ±, DIN (OUT) ±, a LOADI (O) pin and a GND (ground) pin, a total of six lines. Each LED display module PCB contains 64 MAX6974 LED drivers and 512 OVSRRGBCC3 RGB LED.
  Streaming video distribution and control of video frames
  DVI minimum resolution is VGA, QVGA reference design that can be used for interlaced odd or even pixels. TFP401 DVI receiver half pixel clock rate of 12.5MHz. Blanking period of occupation of about 40%. As the MAX6974 interfaces only for odd or even lines, regardless of the blanking period, the serial converter (24-bit RGB) QVGA data rate 12.5/2/1.4 × 24 = 107.142857Mbps. Taking into account DVI 8-bit resolution for each color, each color corresponding to the MAX6974 12-bit converter, the effective data rate of 107.142857 / 8 × 12 = 160.714286Mbps. FPGA cache from TFP401 DVI receiver pixel data flow, data flow is divided into five groups, and then sent to the corresponding LVDS channel. Each LVDS channel data rate of 160.714286 / 5 = 32.1428571Mbps.

TFP401 DVI received by each pixel of each line from left to right, top to bottom of each frame transmission. MAX6974 PWM frame format requirements of each the same color information to a group of 8 pixels transmission (Table 1). Need a store at least eight pixel data buffer supports this format. Taking into account the interlacing and blanking, in order to maintain a fixed transmission speed LVDS channels, reference designs using a video buffer memory data. Buffer may be able to multi-chip MAX6974 devices to connect the two ends of the PCB, to avoid a long right to left using the LVDS link.

Table 1. MAX6974 PWM data in a single frame format header data 1 data 2 data data 3 ... N
HDR [23:0] B7, B6, ... R0 B7, B6, ... R0 B7, B6, ... R0 ... B7 ... R0
B_ ... G_ ... R_ ... 12 位 (MAX6974) or 14-bit (MAX6975) data

  In addition to passing the PWM information for each port, the header CMD bit 010101,101010 and 111111 of the three data frames transmitted by the MAX6974 LVDS interfaces CALDAC, the overall brightness of the PDM, and configuration information (Table 2). Each header contains 24, the first byte synchronization template 11,101,000, followed by six CMD and 10-bit counter value (CNTR). Each port PWM CMD bit data frame is 000000.

 Table 2. MAX6974 data header format for HDR
23 2,221,201,918,171,615 1,413,121,110,987,654,321 0
SYNC CMD CNTR
7 6 5 4 3 2,101,010,109,876,543,210
1 1 1 0 1 0 0 0 C1 C0 C1 C0 C1 C0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

   In addition to PWM information, the data frame is also used PC-based GUI interface to send via DVI. Data within the frame type from the corresponding FPGA circuit identification. Information unrelated to the PWM data frame format shown in Table 3, HDR on behalf of header. Note that each port PWM information does not include the video frame header.

Table 3 video display reference design, data frame screen format line LVDS 1
Pixel 0 至 63 LVDS 2
Pixel 64 至 127 LVDS 3
Pixel 128 至 191 LVDS 4
Pixel 192 至 255 LVDS 5
Pixels, 256-319
0 HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR
1 HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR
2 Chip 1 ... ... Chip 1 ... ... Chip 1 ... ... Chip 1 ... ... Chip 1 ... ...
  .... .... .... .... ....
  .... .... .... .... ....
31 .. Chip 1920 .. Chip 1920 .. Chip 1920 .. Chip 1920 .. Chip 1920
32 HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR
33 HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR
34 Chip 1 ... ... Chip 1 ... ... Chip 1 ... ... Chip 1 ... ... Chip 1 ... ...
  .... .... .... .... ....
  .... .... .... .... ....
63 .. Chip 1920 .. Chip 1920 .. Chip 1920 .. Chip 1920 .. Chip 1920
64 HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR
65 HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR HDR ... HDR
66 Chip 1 ... ... Chip 1 ... ... Chip 1 ... ... Chip 1 ... ... Chip 1 ... ...
  .... .... .... .... ....
  .... .... .... .... ....
95 .. Chip 1920 .. Chip 1920 .. Chip 1920 .. Chip 1920 .. Chip 1920

  Table 3 describes the 320 pixel and 96 pixel video frame control line. 1 至 5 LVDS channel transmission, respectively, 0-63, 64-127, 128-191, 192-255 and 256-319 of the video and control information. In a control video frame, 0 to 1 line each pixel contains 24 header configuration information (HDR); line 32 and line 33 contain the header information PDM overall brightness, the first 64 rows and 65 lines contain CALDAC the header information. The reference design, each header line 2 after line 30 the data corresponding to the LED display module, the PCB 30 lines of information. LVDS provides each particular column 64 pixels per line of information for the transmission of each LED display module on the PCB 64 MAX6974 LED driver information. Each MAX6974 devices, including 24 control each pixel of information, video frame control does not use more than 95 rows of data.
  Video display board control GUI
  GUI (Figure 4) is used to configure all the MAX6974 reference design in the global brightness PDM and CALDAC register. The GUI includes a global setting option, adjust the video display board for all the relevant parameters of the chip, the device also contains a tab character, used to adjust the parameters of each chip. All registers and MAX6974 LED driver settings can be stored to a file, when run-time video display board to download data. Provide an initialization settings file, including the typical parameters of the initial register settings, greatly simplifying the video display board initialization.
图4. MAX6974视频显示板的GUI

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Figure 4. MAX6974 GUI video display board
  GUI window as a separate operation in the Windows operating system. Once enabled, the Write button on the GUI, it will create a video control frame and sends it to the video display board. Video control frames only in accordance with 60Hz refresh rate of video display. Video control video display board frame will occupy the entire screen; the FPGA detects header row and the corresponding control information is sent to the MAX6974 registers. Therefore, the video does not display the contents of the control frames in the video display board. Although the video frame refresh will also pass control information, but the human eye will not notice these updates.
 Program implementation
 DVI receiver board includes TFP401 DVI receiver and AT24C02 EEPROM, in addition to a few bypass capacitors (Figure 5). TFP401 DVI receivers implement SERDES and TMDS decoding, and to ensure that the next pixel clock rate in half while to get RGB bit odd, idol factors. Because DVI determine the minimum screen resolution is VGA, each reference design eliminates the neighboring pixels, interlaced. Half pixel clock for the FPGA is very convenient, allowing it to select the required pixels.
 Identified in the Windows operating system monitor, through the DDC in accordance with I ² C protocol to detect the display. Then, the display in response to its EDID, including manufacturer information and operational information. Similarly, AT24C02 EEPROM LED video display board used to store the EDID information. Manufacturer ID must be from the Video Electronics Standards Association (VESA) for the reference design, to borrow DVI LCD monitors EDID, stored in the AT24C02 EEPROM. When all three address pins grounded, AT24C02 EEPROM's I ² C address is 0xA0, which is the operating system will search for the address.
图5. DVI接收机PCB (2.25&quote; x 4&quote;)
Detailed picture (PDF, 160kB)
Figure 5. DVI receiver PCB (2.25 "x 4")
 FPGA board (Figure 6) consists of two SRAM and an Altera ® FPGA devices. Inside the FPGA with LVDS interface and memory read function. The reference design, FPGA is mainly used for DVI digital video output distribution. Another important role of the FPGA is to identify the data frame configuration, the overall brightness of the PDM and CALDAC information. When the recognition to the video control frame, data frame, in addition to independent PWM information, are received and sent directly to the appropriate down the MAX6974 registers.
图6. FPGA PCB (7.5&quote; x 9.5&quote;)
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 Figure 6. FPGA PCB (7.5 "x 9.5")
 Figure 7 shows the FPGA's internal functional circuit, a pixel data bit is stored in the SRAM cache. FPGA internal row buffer for connection TFP401 DVI and LVDS receiver channels. Two cache lines, one line for receiving data bits received TFP401, another line connecting the SRAM buffer TFP401 DVI receiver for receiving data. Similarly, two lines of buffer for each LVDS channel. FPGA logic to provide a complete DVI and LVDS consistent data throughput, and provide the required SRAM data, address and control signal timing. Because single-port SRAM, and read and write operations need to configure the FPGA internal memory access.
图7. FPGA内部功能模块
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Figure 7. FPGA internal function modules
 Each MAX6974 drives 8 RGB LED, each display module contains 64 MAX6974 LED driver (Figure 8), in accordance with 8 rows, 8 distribution, in addition to 8 lines, 64 of 512 RGB LED. All LED mounted on the side of the PCB, LED center distance of 8mm (up, down, left and right spacing), display module circuit board size is 512mm x 64mm. All MAX6974 devices are installed in the other side of the PCB. MAX6974 devices installed side, laying power and ground, including 1 x 6 connector, 1 x 6 2 groups totaling connectors: one for the upper left corner of the LVDS input interface and one for the lower left corner of the LVDS output interface. Display module circuit board can be embedded in the frame of the video display board, all connected boards are installed in the frame. LED display module adjacent LVDS interface between the PCB does not require additional leads.

图8. LED显示模块PCB (64mm x 512mm)和LED一起装配在一侧,MAX6974 LED驱动器装配在另一侧(PCB分为左侧(a)和右侧(b))。
Detailed picture (PDF, 1.25MB)
 Figure 8. LED display module PCB (64mm x 512mm) and LED assembly with one side, MAX6974 LED driver mounted on the other side (PCB into the left (a) and right (b)).
 Figure 9 shows the general with a DVI receiver, FPGA and PCB 150 LED display module of QVGA LED video display board. The PCB arranged in 5, line 30. DVI receiver and FPGA PCB as shown, install the video display board above, can be easily hidden LED display module to the back of the PCB.

图9. 视频显示板装配图
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 Figure 9. Video display board assembly drawing
 Power
 3.3V VCC supply, each piece MAX6974 operating current of 28mA (CALDAC off) or 54mA (CALDAC enabled). An LED display module on the PCB contains 64 MAX6974 LED drivers, working current of 1.8A or 3.5A. Using 5V VLED supply, MAX6974 Each port provides maximum LED current is 30mA. 512 RGB LED display module of the maximum current of 46A, 3.3V and 5V power supplies that require multiple video display board for the entire power supply.
 80 x 64 LED video modules
 Figure 10 9 LED PCB mounted on a frame (can be installed 10 PCB), FPGA and DVI receiver PCB is mounted on the back (Figure 11). QVGA display boards installed in the 15 (3 x 5) such a framework.

图10. 一块可安装10块LED PCB的框架
Figure 10 one can be installed 10 LED PCB framework

图11. 框架背面
Figure 11 frame back
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