Based on ARM kernel audio decoder system for decryption

  Tang technology professionals provide a reverse technology system solutions, based on the ARM core audio decoder single chip system, to undertake long-term imitation clone with two times the development, and at the same time the products provide a full set of technical information transfer, interested parties please contact with the technology.EP7209 is the world's first to not only support for the popular MP3 standards, such as Microsoft Audio also support the rapid emergence of Internet audio compression standard for digital audio decoder system on chip.
   EP7209 under the 74MHz runtime performance and Intel Pentium chip based on 100MHz personal computer, and the power consumption is very small : the 2.5V voltage, power consumption less than 170mW. Its ARM core provides an excellent digital signal processor can provide processing ability, therefore, Internet audio processing only occupies the 50% chip processing ability. The embedded system design personnel leaves high up to 25MIPS ( millions of instruction per second) processing capability for realizing other functions. This paper mainly discusses the structure of EP7209, function, interface properties and its application in embedded system.
   One, function block diagram and function block descriptionFigure 1 is the EP7209 function block diagram.
   Figure 1 shows the EP7209 contains the following function block.
( 1) the ARM720T processor contains the following function block:ARM7TDMI CPU core. The CPU kernel support Thumb instruction set, kernel debugging, enhancement of the multiplier, JTAG and embedded IE. Its clock rate can be programmed for 18MHz, 36MHz, 49MHz, 74MHz.The memory management unit ( MMU ) and ARM710 nuclear compatible, and added to the Windows CE support. The memory management unit provides address translation and one of the 64 items of converting the bypass buffer.The 8KB offers a single instruction and data cache and a four cache memory controller.The write buffer.
( 2) 38400 bytes on-chip SRAM, in LCD controller and general application sharing between.
( 3) memory and high up to 6 independent extended segment interface, each extension period of 256MB, and wait for the state of programmable.
( 4) 27 general I / O, multiplexing can be, as required to provide additional functionality.
( 5) digital audio interface ( DAI ) can be directly and CD quality DAC and codecs.
( 6) interrupt controller.
( 7) the advanced state of the system control and power management.
( 8) 2 16550A compatible duplex UART, containing 16 bytes to send and receive FIFO.
( 9) the SIR protocol infrared data codec, rate up to 115.2kbps.
( 10) the LCD controller, 16 gray, programmable 1, 2 or 4 bits per pixel.
( 11) film on the initiation of ROM, cured for serial loaded boot code.
( 12) 2 16 universal counter.
( 13) 1 32 real-time clock ( RTC ) and comparator.
( 14) 2 synchronous serial interface, such as ADC Microwire or SPI for peripheral devices. An interface to support the main mode and the slave mode, another only supports the main mode.
( 15) a complete JTAG boundary scan and embedded ICE support.
( 16) 2 programmable pulse width modulation interface.
( 17) 1 for and 1 or 2 Cirrus Logic CL-PS6700 PC card controller device connected to the interface, can support 2 PC card slot.
( 18) oscillator and a phase-locked loop, used by external 3.6864 MHz oscillator generating cores needed for 18.432MHz, 36.864 MHz, 49.152MHz or 73.728MHz clock. In addition to an external clock input terminal ( 13MHz mode ).
( 19) a low power 32.768kHz oscillator, for generating real time clock required 1Hz clock.
  All of the external memory and peripheral devices to be connected to the 32 data bus D [0: 31], and shall use the 28 bits of the address bus A [0: 27] and other control signals.
  The EP7209 core logic function is established in a ARM720T embedded processor. The design of EP7209, with low power consumption for the purpose of optimization, and the use of completely static 0.25 u m CMOS manufacturing process. Low power consumption ideas embodied in the same state design, clock using way. The following will have the option of introducing the working principle of EP7209. ARM720T consists of a ARM7TDMI 32 RISC processor, of a single cache and a memory management unit ( MMU ). 8KB cache has a four item associative registers, and is organized into 512 lines of four characters ( 4 x 512 x 4 bytes). High speed buffer directly connected to the ATM7TDMI, the cache from CPU virtual address. When the desired virtual address is not in the cache, by MMU translates the virtual address to physical address. A 64 study of the conversion of the bypass buffer ( TLB ) is used to speed up the process of the change of address, and reduce the page table reads the desired bus transfer. Only by converting the cache is not stored address, MMU will be able to save power. EP7209 supports the following power management status: operation, idle and reserve (energy ), as shown in figure 2. Normal program execution state of operation state. This is a complete performance state, the clock and peripheral devices are enabled. In addition to the CPU clock is paused, idle state and operation state is the same. An interrupt or wake up will make the idle state is returned to the operating state. Backup state minimum power consumption, choose this model will close the main oscillator, only for the real-time clock and associated logic power supply. When the EP7209 is in a standby state, to ensure that the system can normally wake up, all the power and ground pins are still connected with power and ground is very important. Fallback state can only change to the state 's operation state.
 3 Reset
   EP7209 has three asynchronous reset signal: nPOR, nPWRFL and nURESET. If any of them effectively, a system reset will be generated by internal. In addition to the RTC data and a match register, all of the EP7209 internal register will be reset. In order to make the system time in user reset or power failure condition is maintained, the RTC data and a match register is caused by nPOR reset to remove.Any reduction will reset the CPU, and in EP7209 return operation state to CPU from the reset vector at the beginning of program execution.
  4 Clock
  EP7209 has two clock mode: external clock input and on-chip PLL. Clock source selection is from port E second foot ( PE [2 ] ) a trap options to achieve. If the PE [2 ] at the rising edge of nPOR is high ( such as electricity ), the external clock mode is selected; if PE [2 ] is low, so, on-chip PLL mode is selected. After power on, PE [2 ] can be used as a universal input output port.
   The EP7209 device has several independent logic section, each with its own clock frequency requirements. When the EP7209 is in the external clock mode when the peripheral device, the true frequency will differ from the PLL mode frequency.
  5 interrupt handling
  During the execution of a program, when an unpredictable events (such as interrupt or memory error occurs, usually ) to generate an exception. When the exception occurs at the same time, by the fixed priority service system determines the processing order. Table 1 shows all of the exception priority order.EP7209 interrupt controller has two interrupt types: interrupt request ( IRQ ) and fast interrupt request ( FIQ ). The interrupt controller has the ability to control from 22 different FIQ and IRQ interrupt interrupt. Of these 22, 17 are mapped to the IRQ input, while the other 5 are mapped to the FIQ input source. FIQ IRQ has a higher priority than. If from the same group ( IRQ or FIQ ) the two interrupt is received, the service order must be made by the software to solve. All interrupt is level sensitive, that is to say, they must be consistent with the following order.
  ( 1) interrupt device ( internal or external ) to generate the appropriate interrupt.
  ( 2) if the interrupt mask register appropriate bit has been set, then a FIQ or IRQ will be generated by the interrupt controller.
  (3 ) such as the interrupt is enabled, the processor fault scheduling software to read the interrupt status register to determine the source of the interrupt, and call the appropriate interrupt service routine.
  ( 5) the interrupt service routine in the software will clear the interrupt source, which is based on the request interrupt device take some by the device specific actions to implement (e.g., read UART RX register ).
   Then, the interrupt service routine to enable interrupt. Any unhandled interrupt will be in the same way is service. Or, it can be returned to the interrupt dispatch software. This software can examine any unhandled interrupt and corresponding scheduling them. " End of Interrupt" type of interrupt will be latch. All other interrupt source ( such as an external interrupt source ) must remain valid until the corresponding service routines, started.
  6 EP7209 boot mode
   On chip to start the ROM 128 byte contains a sequence of instructions. The sequence of instructions to initialize the device, and then configure UART1 to receive a 2048 byte serial data. These data received will be placed on the SRAM. Once the download is complete transmission, execution will jump to the on-chip SRAM start. This will allow such as in product manufacturing process code and programming to the Flash in such operations.
  Whether from the on-chip boot ROM system is composed of nMEDCHG pins in power during reset state decision. If the effectiveness of nPOR, nMEDCHG, then, EP7209 will connect to the CS [0 ] of the external memory device startup ( normal mode ); if nMEDCHG is low, then, starting from the on-chip ROM began. Note: in two cases, power on reset after the end, EP7209 will is in a standby state, and in order to really start execution start sequence, required in the WAKEUP pin has a low to high jump.
   On chip ROM is the result of all the chip select decoder have turned. Start options control signals from the nPOR latch, which means the address and bus width remapping will continue to apply, until the nPOR again effective. From the ROM after the start, start the ROM content can be obtained from the address 0x0000000 read back; and under normal operating conditions, start the ROM content can be obtained from the address range 0x70000000 read back.
  The 7 memory and I / O extended interface
EP7209 is able to decode 6 discrete linear memory or extended period. One of the two available for PC Card card reservation, each interface is connected to an independent single CL-PS6700 device. Each segment size 256MB. Two additional segments ( except for the 6 paragraph beyond) was used for on-chip SRAM chip and ROM. On chip ROM space has been completely decoded, SRAM space has also been completely decoded to programming in the LCDCON register in the video frame buffer in the maximum capacity ( 128KB ). Beyond this address range SRAM space not to be fully decoded (i.e., beyond the scope of any access to 128KB back to 128KB range ). The 6 section in either may be configured with traditional SRAM interface consistent interface is connected, and can be individually programmed for 8, 16 or 32 bits wide, support page mode access, and in the implementation of non continuous access can be inserted into the 1 ~ 8 waiting state, execute trigger mode access can be inserted into the 0. The 3 waiting state. Zero wait state continuous access characteristics is designed to support the ROM trigger mode. On the use of the nMWE pin writable memory device, not allowed to zero wait state continuous access, at least should be inserted into a wait state ( wait state number should be programmed into the appropriate MEMCFG register in continuous domain ). Bus cycle can also be through the use of the EXPRDY input signal to extend.
  8 big end and the small end configuration configuration
   EP7209 on the internal registers using the small end ( little endian ) configuration. However, connecting device to use big end ( big endian ) configuration of an external memory system is possible. The ARM720T control register in the big / small end bit set EP7209 in the treatment of memory's word is in big-endian or small end format. Memory is considered from 0 onward numbered byte linear combination. Byte 0 ~ 3 accommodate first was stored word, byte 4 ~ 7 containing second words, etc.. In the small end in the program, the lowest numbered byte in the word that is the word most significant byte, and the highest numbered byte is considered to be the most high byte word. Byte0 storage system in this program should be connected to the data line 7 to 0 ( D [7: 0] ). In the main program, word of the top byte is stored at the lowest numbered byte, and the minimum number of bytes to be stored in the highest byte. Therefore, the memory system of Byte0 should be connected to the data line 31 to 24 ( D [31: 24] ). Load and store instructions are size end configuration affects only instruction.
  9 support the on-chip frame buffer LCD controller
   LCD controller provides all the necessary control signals to direct with a single panel composite LCD interface. The size of the panel is programmable, is in the 16 pixel increments, from 32 to 1024 pixels of any width ( length ). Total video frame buffer size can be programmed for high amounts to 128KB. This equates to a theoretical maximum of 1024 x 256 pixels panel size ( 4 bits per pixel ). The video frame buffer can be located in any one of the control memory chip select. In any one chip under the control of the memory start address, it is fixed to the address of 0X00000000. LCD video frame buffer start address register definition in FBADDR [3: 0], these will become the most important external address bus nibble ( byte ). The default start address for the 0XC0000000 ( FBADDR = 0XC ). The use of a piece of SRAM ( OCSR ) to establish the system will pass the on-chip SRAM for LCD video frame buffer and used for a variety of data storage. LCD video frame buffer start address in this system should be set to 0X6.
  In three, the memory mapping
  The address space of the low 2GB