Analysis of a number of key asked about DSP programming board copy board

  In the actual communication applications, a burst, the program for the next burst must prepare. Therefore generally use the serial port DMA multiple-frame mode, but some of the issues to be discussed but the serial port to transfer data by DMA. First DMA transfer synchronization events should be located McBSP transfer events XEVT, after a byte transmission will automatically prepare another byte (McBSP READY rising edge triggered DMA transfer). Mean to interrupt occurs, a block transfer completed, when the DMA is enabled automatically shut down McBSP the READY will continue to maintain a high state. But the next burst transfer directly enable DMA Shique not start transmission (I believe there will be many I encountered such problems). This is because they can not produce the the McBSP trigger needed to start READY rising edge. The solution is in the interrupt routine to close McBSP send READY = "0", then send program to enable DMA then open the McBSP transmitter can be. pcb copy board, such as Open McBSP send first to open DMA, also will not work. Because the McBSP READY 0 to 1, and can no longer produce READY rising edge.
    2 Turn off the difference between DMA Close McBSP
    In the field of communication, in order to take full advantage of the DSP on-chip peripherals resources, often using DMA from the data to the serial port, or to send data into the buffer, and then processing. The DMA in the data buffer pointer points to the location of the interruption occurred, an interrupt is generated. But the last data just entered the McBSP has not really sent out, only to close the DMA transfer end interrupt program can not be closed McBSP. Because the McBSP hair register DXR word, no issue.
    3 McBSP serial port configuration of critical timing
    Mainly the configuration register SPCR2: keep RRST, XRST, FRST you configured serial port control register 0 premise. Wait at least two CLKR / T clock to ensure that the DSP internal synchronization.
    (1) can be loaded to DXR data or enable DMA.
    (2) to enable GRST (GRST = 1) (if necessary DSP internal sampling clock).
    (3) to enable RRST or XRST, and to pay attention to ensure that at this time the SPCR, only this one change.
    (4) Enable FRST (FRST = 1) (If you need to DSP internal frame synchronization).
    (5) Wait 2 R / T CLK clock cycles after the closing or the originator will be effective.
    4 variables in assembly language programming
    The public assembly language program variables should be defined in the file, such as. def carry. Shenzhen pcb copy board assembly language program to use local variables without definition, can direct statement such trn_num, word 00h. If both defined variables of the same name in two asm file, the compiler would think that the points they are not the same variable. Should be in the beginning of the assembler. mmregs macro statement. It said on the one hand, on the other hand can be used to register redefine default definition of confirmation (ah, bh, trn). Such as: mmregs DMPREC. set 54h; defined DMA priority and enable register address 54h DMSA. set 55h DMSDN. set 57h DXR10 set 23h; definition serial transmit register to eye in 23h
    CPL bit 5 ST1 register
    CPL bit the compilation mode control bit, it indicates which pointer relative direct addressing. When CPL = 0, the use of the page pointers DP; When CPL = 1, using the stack pointer SP. There is no difference in actual use in both, but use SP addressing the program more readable. Is frequently used in the program CPL = 1.
    6 instruction of ambiguity
    6.1 Compare the following the instructions STLM B AR4; to bl contents into the register AR4 (x)
    STLM B, * AR4; to bl contents into the register AR4 (√)
    The former actual implementation is bl content into a system buffer, which is also available: MVDM BL, AR4; to bl contents into the register AR4 (√)
    Other easily lead to ambiguous statement:
    LD AR5, A; the AR5 the contents into the register A (x)
    LDM AR5, A; put the AR5 the contents into the register A (√)
    ANDM # 0x107e, AR4; the # 107e applied to register AR4 (x)
    ANDN # 0x107e, * AR4; the # 107e applied to register AR4 (√)
    Only certain registers of effective instruction:
    The MVDD * AR2 +, * AR3 +; copyed of AR3 AR2 for the contents of the address such an instruction is used as the address data block move is particularly effective, but only the AR2, AR3, AR4, AR5 effective.
    The program run harm fallibility statement is:
    ST # 0, * (bsp0_out_sign); bsp0_out_sign a variable name (√)
    The STM # 0, bsp0_out_sign; This statement is compiled STM # 0, the PMST or STM # 0, IMR (×)
    This statement will cause the program to run in the random failure, and is extremely difficult to find.